1. Field of the Invention
This invention relates generally to a method for fabricating MOS transistors and more particularly, to a method for fabricating low threshold voltage N-channel and P-channel MOS, and CMOS transistors in integrated circuits.
2. Description of the Related Art
Among numerous silicon MOS transistors, CMOS devices formed by the combination of PMOS and NMOS transistors are widely used in view of the low quiescent power consumption and high integration density features.
As the demand for low power consumption has increased, lower supply voltages have become more requisite for CMOS devices. This necessitates that the MOS transistors be operated at lower threshold voltages and this gives rise to the problem such as the increase in power consumption caused by subthreshold leakage currents and the short channel effects.
In the conventional MOS process, a CMOS device is fabricated with gate electrodes of N conductivity type (N-type) polysilicon. However, since a PMOS transistor of the CMOS device is generally designed to be of the buried channel type to facilitate the control threshold voltages, relatively large short channel effects and subthreshold currents are induced in the PMOS transistor because of the buried channel structure.
By contrast, when a gate electrode of the PMOS transistor is composed of P-type polysilicon, the short channel effect can be suppressed since the PMOS may be operated as a surface channel type MOS transistor.
Although either boron (B) or boron difluoride (BF.sub.2) may be used as dopants for forming the P-type polysilicon electrode, boron has been used conventionally for the following reasons: The decrease in threshold voltages and device reliability of the PMOS have been found. This is considered to be due to the B penetration into a channel region through a gate oxide layer which is caused by the difference in the amount of B segregation affected by fluorine at the interface between silicon (i.e., channel region) and silicon oxide (gate oxide layer). Therefore, the B dopants have been used conventionally for gate electrode doping. In addition, this B doping has been carried out simultaneously to the source and drain regions of PMOS transistors as well.
However, by this B doping method to the source and drain regions, the formation of shallow junctions in the source and drain regions is difficult, as aforementioned, which is disadvantageous to the device miniaturization. Furthermore, although this B doping is preferred for the fabrication of high withstand voltage MOS transistors, its allowable range in doping concentration is rather limited and can not be decreased enough due to the induction of the carrier depletion in polysilicon gate regions.
Referring to FIGS. 7A through 7D, there are described prior art process steps for fabricating low threshold voltage MOS transistors.
There are formed P-well and N-well regions 2 and 12 on a silicon substrate 1 in the regions 16, 17 and 18 where NMOS and PMOS transistors are to be formed, respectively, as shown in FIG. 7A.
A field oxide layer 4 of silicon oxide for isolation is then formed on a main surface of the well regions by the conventional local oxidation of silicon (LOCOS) process, in which openings for the NMOS and PMOS regions are defined using an oxidation mask film (not shown). Thereafter, a gate oxide layer 3 is formed, wherein channel doping is carried out so as to control threshold voltages of each MOS transistor.
Subsequently, a layer of polysilicon 5 for forming gate electrodes is disposed on the gate oxide layer 3. Since this polysilicon layer is also utilized as a resistor for an analogue circuit which will be described hereinbelow, the entire surface of the polysilicon layer 5 is doped with appropriate impurity ions so that predetermined values of resistivity can be obtained. This doping is usually carried out by implanting phosphorus (P) ions to facilitate the feasibility of the predetermined values.
As illustrated in FIG. 7B, a first mask 6 is provided over both the resistor and the region where a PMOS transistor 18 is to be formed. Subsequently, to dope the area of the polysilicon layer exposed by the first mask 6, a doping step is carried out with a high concentration of P ions either by ion implant or thermal diffusion process at from 900.degree. to 1000.degree. C. As the mask 6, a photoresist layer is conventionally used for the ion implant, while a silicon oxide layer is used for the thermal diffusion process. By this heavy P doping, the exposed portion of the polysilicon layer 5 turns to an N.sup.+ polysilicon layer 7.
By subjecting the polysilicon layers 5 and 7 to a patterning process using the conventional photolithography technology, a gate electrode 7a of NMOS transistor 16, gate electrodes 7b and 5 of PMOS transistors, and a resistor layer 5 are defined, as shown in FIG. 7C. Subsequently, a second mask 10 is provided to cover a predetermined portion except for the NMOS transistor 16 to be formed, and a high concentration of N-type impurities are doped to form source and drain regions 14 and 14 of the NMOS transistor 16.
Referring to FIG. 7D, a third mask 11 is provided to cover a predetermined portion except for the PMOS transistors 17 and 18 to be formed, and a high concentration of P-type boron impurities are doped to form source and drain regions 15 and 15 of the PMOS transistors 17 and 18, and the gate electrode 9 of PMOS 18.
To proceed with the miniaturization of the MOS transistor devices, the reduction in short channel effects is quite important. This may be carried out effectively by forming relatively shallow junctions for source and drain regions.
It has been known that although the source and drain regions may generally be formed for PMOS transistors by doping either B ions or BF.sub.2 ions, the latter ions are preferred for forming shallow junction regions and resulting in greater reduction in the short channel effects.
As described earlier, however, in the prior art ion implant process which has been carried out simultaneously into source and drain regions 15 and 15 and gate electrode 9, BF.sub.2 ions may not be selected for this ion implanting step for the following reasons:
When BF.sub.2 ions are used for a heavy doping into a gate electrode region, this doping is known to give rise to (1) a reduction of threshold voltages caused by B ions which reach even to a channel region by the enhanced diffusion effect assisted by the presence of F ions, and (2) the reduced reliability of a gate electrode 3 caused by a relatively large amount of B ions diffused into the gate electrode.
Accordingly, BF.sub.2 ions can not be used for this doping step, and it has been difficult to form shallow source and drain regions 15 and 15 on the surface of the semiconductor substrate, thereby resulting in an unwanted increase in the short channel effects.
In addition, to fabricate a PMOS transistor having a withstand voltage on the order of 10 V, in general, the impurity concentration in the drain region has to be lowered, since a withstand voltage is primarily determined by the breakdown voltage caused by the field concentration at the edge of the drain.
However, the above-mentioned lowering of the impurity concentration gives rise to another problem for the PMOS device, in that, by the use of a P.sup.+ polysilicon layer for the gate electrode of the PMOS device, the carrier depletion in the gate region is induced with relative ease by the lowered concentration.
In other words, this problem of the PMOS device arises when the impurity concentration is lowered in the interface region between P.sup.+ polysilicon layer and gate oxide layer for the gate electrode, due to the following factors: (1) The carrier depletion is induced at the gate oxide side of the polysilicon layer, and (2) this results in an insufficient channel formation because of the unduly reduced electric field at the polysilicon (gate) electrode, thereby resulting in a decrease in transconductance (gm) of the PMOS transistor.
This problem may be obviated by optimizing the conditions for fabricating MOS transistors, such as concentration and distribution of the impurities, and the conditions may vary depending on, among others, the thickness of the polysilicon layer. For the polysilicon layer thickness of about from 300 to 400 nm, for example, the appropriate conditions may preferably be achieved by carrying out an implant with ions of a concentration of approximately from 2.times.10.sup.15 to 3.times.10.sup.15 cm.sup.-2 and a thermal annealing at temperatures approximately from 850.degree. to 900.degree. C. These conditions are chosen such that the implanted ions will not penetrate through the gate oxide layer.
However, these conditions have not been achieved by prior process steps as described earlier. Therefore, the impurity concentration at the drain edge has not been optimized, and withstand voltages high enough for practical use have not been achieved for the MOS transistors.